Poster VTC

CMOS

When input voltage is smaller than threshold voltage, the NMOS is off and PMOS is in non-saturation region, hence the output voltage equals to VDD. When input voltage just grows larger than threshold voltage, NMOS is biased in saturation region and PMOS is still in the non-saturation region, there is a current flowing in the CMOS. The output voltage begins to drop from VDD. Then the input voltage continues to grow, both NMOS transistor and PMOS transistor are in saturation region. The output voltage will fall sharply. After that the NMOS is biased in non-saturation and PMOS continues to be in saturation region, the output voltage will drop slowly until input voltage reaches VDD-VTP. When input voltage equals to VDD-VTP, the PMOS is off, NMOS is closed and the Vout is 0, there is no current between VDD and GND.

This figure shows the voltage transfer curve of silicon CMOS of different aspect ratios, W/L.It can be oberved that with the aspect ratio of n-channel transistor increases, or aspect ratio of p-channel decreases, the curves moves left, which means the input voltage where both n-channel and p-channel transistor saturate is smaller.This is because when aspect ratio becomes smaller, the current in the transistor decreases then the resistance increase, thus the voltage that applied to the transistor increases. It is known that the p-channel transistor's input voltage is VDD minus input voltage of CMOS and VDD is unchanged, thus if the voltage across p-channel transistor increases, the input voltage of CMOS decreases. That explained the shift of the voltage transfer curves.

This is the figure that describe voltage transfer curves of silicon CMOS and organic CMOS. In this case, the holes mobility is twice of the electrons mobility in organic device, contrary to the situation in silicon MOSFET. Because the holes mobility is larger, the effective resistance is smaller thus the voltage is larger. When VDD does not change, the input voltage needs bigger value to reach saturation region. This is why the voltage transfer curve of organic CMOS is on the right of the silicon voltage transfer curve.

PMOS (Enhancement-load)

A enhancement-load MOSFET is constructed by a load transistor with gate connected to the drain and a driver transistor with the same type of the load transistor. The load transistor always operates in the saturation region. When input voltage is less than threshold voltage of driver transistor, the driver is cuoff and the drain currents are zero. The highest output voltage is VDD minus threshold voltage of load transistor because the load is always saturates. After input voltage grows larger than threshold voltage of driver, the output voltage decreases linearly when input voltage increases. When input voltage reaches the value where driver transistor saturates, the output voltage decreases non-linearly with input voltage increases until the lowest output voltage is obtained.

The figure above displays the voltage transfer curves of PMOS under different aspect ratio of driver and load transistor. Smaller aspect ratio leads to higher curve with larger final output voltage. This is because with the aspect ratio of load transistor decreases the voltage across load increases, even the input voltage reaches the value that cuts off the driver transistor, the output voltage will have some value that always saturated load transistor contributes. Also, the slope of linear region is decided by the aspect ratio of load and driver transistor. The voltage drops sharply when large aspect ratio of driver is applied.

These are voltage transfer curves of organic PMOS under different aspect ratio of driver and load. The organic enhancement-load inverter is applied special equations to conduct the curves, although the shape of curves are similar to the silicon ones. The highest output voltage is also VDD minus threshold voltage of lead transistor and the lowest output voltage is determined by the aspect ratio of load and driver transistor.